1. Field of the Invention
The present invention relates to an active type photoelectric conversion device using a metal-oxide-semiconductor field effect transistor (MOSFET). More particularly, the present invention relates to an active type photoelectric conversion device which can realize an excellent performance and a lower driving voltage, a method for fabricating such an active type photoelectric conversion device, and an active type solid-state imaging device using such an active type photoelectric conversion device.
2. Description of the Related Art
A charge-coupled device (CCD) where signal charges themselves generated in respective pixels are read is currently the most popular among other photoelectric conversion devices. An active type photoelectric conversion device has recently been proposed to replace the CCD, where signal charges are first amplified in respective pixels and then sequentially read by a scanning circuit. By the amplification of signal charges in the respective pixels, a sufficient amount of signal charges for reading can be secured and the dynamic range becomes broader than that of the CCD. Moreover, in such a device, the signal charges can only be read by driving the horizontal and vertical lines, as well as selective switches connected to pixels to be read, with a smaller voltage. Therefore, a smaller amount of power consumption is required than that of the CCD.
In such a photoelectric conversion device, a transistor is generally employed to amplify the signal charges in a pixel. Transistors are classified into a SIT type, a bipolar type, a FET type (a MOSFET or a junction type FET), and the like. In the SIT type and the bipolar type, the transistor structure is formed in the depth direction of a semiconductor substrate, while in the MOSFET type it is formed along the surface of the semiconductor substrate. The MOSFET type therefore provides a simpler configuration and easier fabrication for the formation of scanning circuits for pixels.
It is advantageous to use a device in which a single MOSFET is contained inside a pixel in order to increase the pixel density. A charge modulation device (CMD) type, a floating gate array (FGA) type, a bulk charge modulated device (BCMD) type, and the like have been reported as examples of devices having a single FET in each pixel.
FIGS. 9A and 9B show pixels of a conventional CMD type active type photoelectric conversion device. FIG. 9A is a plan view of the pixels, and FIG. 9B is a sectional view taken along line 9B--9B of FIG. 9A. The CMD type photoelectric conversion device is described in Nakamura et al., "Gate-accumulation type MOS phototransistor image sensor", 1986 Television Academy, p. 57.
As shown in FIG. 9B, an n-type well 102 is formed as a buried channel in a p-type substrate 101. A gate electrode 104 is formed on the n-type well 102 with an insulating film 103 therebetween. A source region 105 and a drain region 106, composed of a highly-concentrated n-layer and separated by the n-type well 102, are formed in the n-type well 102 at the surface thereof.
As shown in FIG. 9A, the gate electrodes 104 of the respective pixels are connected in common to gate terminals 107 in a horizontal direction, and the source regions 105 are connected in common to source terminals 108 in a vertical direction. The drain regions 106 form a mesh pattern and are connected to drain terminals 109. In this way, the pixels are arranged in a matrix, so as to complete the CMD type active type photoelectric conversion device.
The operation of the CMD type active type photoelectric conversion device will be described.
FIG. 10 shows a potential distribution in the depth direction of the device along line 10--10 of FIG. 9B. First, at the signal accumulation, a gate voltage V.sub.L is applied to the gate electrodes 104 of the pixels lined in a horizontal row via the gate terminal 107. By this application of the gate voltage, signal charges (holes) generated by photoelectric conversion are accumulated at an interface between the semiconductor (n-type well 102) and the insulating film 103 in the pixels.
At the signal reading, the gate voltage is increased to a voltage V.sub.M from the voltage V.sub.L. In response to this voltage change, a current flows between the drain region 106 and the source region 105 of each transistor. The current value changes depending on the amount of the accumulated signal charges. The changed current value is read via the source terminal 108 as a signal output. Signal charges accumulated in the other pixels connected to the same source terminal 108 are not read because the gate voltage V.sub.L is applied to the gate electrodes 104 in these pixels via the other gate terminals 107.
When the accumulated signal charges in the pixels are cleared, the gate voltage is changed to a voltage V.sub.H, so as to provide a potential gradient where the voltage monotonously decreases in the depth direction. This allows the signal charges (holes in this case) accumulated at the interface between the n-type well 102 and the insulating film 103 to be drained right below toward the p-type substrate 101 as shown by dash-line arrows in FIG. 9B. This also serves as the reset for the next signal accumulation.
FIG. 11A is a sectional view of a pixel of a conventional FGA type active type photoelectric conversion device. FIG. 11B shows a potential distribution in the depth direction of the device along line 11B--11B of FIG. 11A. The prior art device shown in these figures is described in J. Hynecek, "A New Device Architecture suitable for High-Resolution and High-Performance Image Sensor", IEEE Trans. Elec. Dev. Vol. 35, No. 5, p 646 (1988).
The FGA type photoelectric conversion device is different from the CMD type one in that a p-layer 110 with a high impurity concentration is provided on the n-type well 102 under the gate electrode 104, as shown in FIG. 11A.
A gate voltage is set to be V.sub.L at the signal accumulation and the signal reading, and the variation in the channel potential at the n-type well 102 in accordance with the accumulation of the signal charges in the p-layer 110 is detected and read as a variation in the threshold value. The other pixels on the same signal line are not detected because the gate voltage is in a V.sub.L level only at the signal reading.
At the resetting, as in the case of the CMD type one, the gate voltage is set to be V.sub.H, so as to provide a potential gradient where the voltage monotonously decreases in the depth direction. This allows the signal charges accumulated in the p-layer 110 to be drained right below toward the p-type substrate 101.
FIG. 12A is a sectional view of a pixel of a BCMD type active type photoelectric conversion device. FIG. 12B shows a potential distribution in the depth direction along line 12B--12B of FIG. 12A. The prior art device shown in these figures is described in J. Hynecek, "BCMD--An Improved Photosite Structure for High Density Image Sensor", IEEE Trans. Elec. Dev. Vol. 38, No. 5, p 1011 (1991).
As shown in FIG. 12A, each pixel of the BCMD type photoelectric conversion device includes a p-layer 112, an n-layer 113, and a p-layer 114 stacked in this order on an n-type substrate 111. P-layers 115 with a high impurity concentration are formed as source and drain electrodes to reach the p-layer 112 through the n-layer 113 and the p-layer 114.
The BCMD type photoelectric conversion device is different from the FGA type one in the following points: (1) The signal charges are converted into electrons and accumulated in the buried channel n-layer 113; (2) The potential variation at the p-layer 114 caused by the signal charges is detected as a variation in the threshold value of the p-MOS structure; (3) At the resetting, the gate voltage is set to be the lower voltage V.sub.L to drain the signal charges to the n-type substrate 111. With these features, the complete transfer of the signal charges is accomplished.
However, the above CMD type, FGA type, and BCMD type photoelectric conversion devices have a problem in that the driving voltages are high. In order to overcome this problem, the inventors of the present invention have proposed an active type photoelectric conversion device which can lower the driving voltages by providing two different gates in each pixel (Japanese Laid-Open Publication No. 8-78653). Hereinbelow, this type of photoelectric conversion device is referred to as a twin gate MOS image sensor (TGMIS) type photoelectric conversion device.
FIG. 13A is a sectional view of a pixel of a conventional TGMIS type active type photoelectric conversion device.
Referring to FIG. 13A, a first gate electrode 123 and a second gate electrode 124 are formed on a p-type semiconductor substrate 121 with an insulating film 122 therebetween. An n-layer 125 is formed in a surface portion of the semiconductor substrate 121 under the first gate electrode 123, and a pair of n.sup.+ -type diffusion layers are formed in the n-layer 125, forming a source region 126 and a drain region 127 of an MOSFET with the first gate electrode 123 serving as a gate. The source region 126 of each pixel is connected to a common source terminal 128, while the drain region 127 of each pixel is connected to a common drain terminal 129.
In the above structure, light h.nu. incident through the first gate electrode 123 generates electron-hole pairs by photoelectric conversion, and the generated electrons flow into the drain region 127. The holes are confined by a barrier formed in the middle of the n-layer 125 and a barrier formed under the second gate electrode 124, and turned into signal charges accumulated at the interface between the n-layer 125 and the insulating film 122. The potential at the n-layer 125 varies in accordance with the amount of the signal charges. This variation of the potential is detected and read as a potential variation at the source region 126 and regarded as an output signal. At the resetting, the potential barrier formed under the second gate electrode 124 is reduced to allow the signal charges to be drained to the p-type semiconductor substrate 121 via a route shown by the dash-line arrow in FIG. 13A.
FIG. 13B shows potential distributions in the depth direction of the device along lines 13B.sub.A --13B.sub.A and 13B.sub.B --13B.sub.B of FIG. 13A. Solid lines 131, 132, 133, and 134 represent the potential distribution obtained along line 13B.sub.A --13B.sub.A, while dash lines 135 and 136 represent the potential distribution obtained along line 13B.sub.B --13B.sub.B.
At the accumulation of the signal charges, a negative voltage V.sub.A (L) is applied to the first gate electrode 123, while a positive low voltage V.sub.B (L) is applied to the second gate electrode 124. The amount of the signal charges (holes) accumulated at the surface of the n-layer 125 under the first gate electrode 123 varies from zero to a saturation level. With this variation, the potential distribution under the first gate electrode 123 changes from the state shown by the solid line 131 to the state shown by the solid line 132. On the contrary, the potential distribution under the second gate electrode 124 does not change, keeping the state shown by the dash line 135.
A potential difference .DELTA.V.sub.P between the potential value at the crossing of the solid line 131 and the dash line 135 and a surface potential of the semiconductor substrate 121 serves as a barrier for preventing charges from flowing from the semiconductor substrate 121 when no signal charge is accumulated. A potential difference .DELTA.V.sub.Q between the potential value at the crossing of the solid line 132 and the dash line 135 and a potential at the surface of the semiconductor substrate 121 in the state shown by the solid line 132 serves as a barrier corresponding to the saturation level of the signal charges, allowing excessive signal charges to override the barrier to be drained to the semiconductor substrate 121.
At the reading of the signal charges, a voltage V.sub.A (H) higher than the voltage V.sub.A (L) is applied to the first gate electrode 123, while a voltage V.sub.B (H) higher than the voltage V.sub.B (L) is applied to the second gate electrode 124. With this change of the applied voltage to the first gate electrode 123, the potential distribution under the first gate electrode 123 changes from the state shown by the solid line 131 to the state shown by the solid line 133 if no signal charge has been accumulated under the first gate electrode 123. If signal charges have been accumulated to the saturation level, the potential distribution under the first gate electrode 123 changes from the state shown by the solid line 132 to the state shown by the solid line 134. On the contrary, the potential distribution under the second gate electrode 124 changes from the state shown by the dash line 135 to the state shown by the dash line 136 depending on the change of the applied voltage to the second gate electrode 124.
Assume that the potential values at the bottom of the solid lines 133 and 134 are voltages V.sub.SO and V.sub.SM, respectively. When a constant current load is connected to the source region 126 and a voltage V.sub.D higher than the voltage V.sub.SM is applied to the drain region 127, the potential at the source region 126 is either the voltage V.sub.SO or V.sub.SM depending on whether or not signal charges have been accumulated (i.e., depending on the solid line 133 or 134). Thus, an output depending on the amount of the signal charges can be obtained.
A potential difference .DELTA.V.sub.R between the potential value at the crossing of the solid line 134 and the dash line 136 and a potential at the surface of the semiconductor substrate 121 in the state shown by the solid line 134 serves as a barrier for preventing signal charges below the saturation level from flowing into the semiconductor substrate 121. A potential difference .DELTA.V.sub.T between the bottom of the solid lines 132 and 133 serves as a barrier which allows a current to flow only into the source region 126 of the pixel for reading but not into the source region 126 of the pixel for accumulation when the source regions 126 of the pixel for reading and the pixel for accumulation are connected to a common source terminal.
At the resetting, the voltage V.sub.A (H) (the voltage applied at the reading) is applied to the first gate electrode 123, while the voltage V.sub.B (L) (the voltage applied at the accumulation) is applied to the second gate electrode 124. With this application, the surface potential at the semiconductor substrate 121 under the second gate electrode 124 is lower than the surface potential at the n-layer 125 under the first gate electrode 123 by at least .DELTA.V.sub.F. This allows all the signal charges (holes) accumulated in the surface portion of the n-layer 125 under the first gate electrode 123 to be drained to the semiconductor substrate 121 via a route under the second gate electrode 124.
The potential difference .DELTA.V.sub.F is more than zero and represents the relationship between the potentials at the surfaces of the semiconductor substrate 121 under the first gate electrode 123 and the second gate electrode 124 (shown by the solid line 133 and the dash line 135) required for complete drainage of the signal charges at the resetting.
For the quantitative representation of the above TGMIS type active type photoelectric conversion device, Condition 1 as follows is assumed.
Condition 1!
Impurity concentration of substrate: N.sub.B =1.0.times.10.sup.15 cm.sup.-3 PA0 Impurity concentration of n-layer: N.sub.N =3.0.times.10.sup.15 cm.sup.-3 PA0 Thickness of n-layer: d.sub.N =1.5 .mu.m PA0 Thickness of oxide insulating film: d.sub.o =80 nm (first and second gate electrodes 123 and 124 have the same thickness) PA0 Amount of signal charges at saturation level: Q.sub.SAT =5.times.10.sup.11 cm.sup.-2 PA0 Material of first and second gate electrodes 123 and 124: n.sup.+ -doped polysilicon film
The voltages shown in FIG. 13B are set as follows:
V.sub.A (L)=-3.0 V, V.sub.A (H)=0.0 V PA1 V.sub.B (L)=1.0 V, V.sub.B (H)=5.0 V PA1 .DELTA.V.sub.P =0.78 V PA1 .DELTA.V.sub.Q =0.5 V PA1 .DELTA.V.sub.R =0.58 V PA1 .DELTA.V.sub.T =0.74 V PA1 .DELTA.V.sub.F =0.25 V
The voltage difference .DELTA.V.sub.P should be preferably about 0.8 V or more for preventing charges from flowing in. The voltage difference .DELTA.V.sub.Q should be preferably about 0.5 V or less for allowing excessive charges to be drained. The voltage difference .DELTA.V.sub.T should be preferably 0.7 V or more for distinguishing the ON-OFF characteristics of pixels for reading and pixels for accumulation. The voltage difference .DELTA.V.sub.F requires to be 0.0 V or more where no barrier is formed. The above values for .DELTA.V.sub.P, .DELTA.V.sub.Q, .DELTA.V.sub.R, .DELTA.V.sub.T, and .DELTA.V.sub.F are therefore within the preferable ranges. This is because the set values of the voltages V.sub.A (L), V.sub.A (H), V.sub.B (L), and V.sub.B (H) are appropriate.
As described above, the conventional TGMIS type active type photoelectric conversion device has two gate electrodes in each pixel, and the driving voltages V.sub.A (L), V.sub.A (H), V.sub.B (L), and V.sub.B (H) can be set low. However, the combination of these driving voltages V.sub.A (L), V.sub.A (H), V.sub.B (L), and V.sub.B (H) includes both positive and negative voltages, complicating the configuration of the power sources for driving the photoelectric conversion device of this type.
An objective of the present invention is to provide an active type photoelectric conversion device which can be driven only by positive voltages, while maintaining the advantage of the aforementioned TGMIS type photoelectric conversion device of providing low driving voltages, and which can sufficiently suppress the generation of after images and reset noise. Other objectives of the present invention are to provide a method for fabricating such an active type photoelectric conversion device and provide an active type solid-state imaging device using such an active type photoelectric conversion device.